`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/24 12:34:06
// Design Name: 
// Module Name: registers
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module registers(
    clk,reset_n,nop,rs1,rs2,rd,data,data_1,data_2,op_rd
    );

    input clk,reset_n,nop;
    input [4:0] rs1,rs2,rd;
    input [31:0] data;
    input [1:0] op_rd;
    output reg [31:0] data_1,data_2;

    reg [31:0] registers[31:0];

    always @(posedge clk,negedge reset_n) begin
        if(~reset_n) begin
            registers[0] = 32'b0;
            registers[1] = 32'b11;
            // registers[2] = 32'b11;
            registers[3] = 32'b1011;
            registers[4] = 32'b100;
            // registers[5] = 32'b100;
            // registers[6] = 32'b1011;
            //registers[7] = 32'b0;
            // registers[8] = 32'b0;
        end
    end

    always @(posedge clk) begin
        if(nop) begin
            data_1 <= 32'bx;
            data_2 <= 32'bx;
        end
        else begin
            data_1 <= registers[rs1];
            data_2 <= registers[rs2];
        end
    end

    always @(negedge clk) begin
        if(op_rd==2'b00||op_rd==2'b01||op_rd==2'b10)
            registers[rd] <= data;
    end
endmodule
